1. Field of the Invention
The embodiments disclosed in this application generally relate to processes for depositing a contact barrier layer on an integrated circuit (IC) substrate.
2. Background of the Invention
In the formation of integrated circuit structures, an insulating layer is formed over active devices, or over a patterned underlying metal interconnect layer, and vertical openings are then formed through this insulating layer to provide electrical communication from the upper surface of the insulating layer to the underlying active device or electrical interconnect. Such openings are then filled with an electrically conductive material to provide electrical connection between the underlying elements and conductive materials, such as a metal interconnect, subsequently formed on the surface of the insulating material. In the fabrication of both horizontal and vertical interconnects, barrier layers are typically deposited over the patterned surface of a substrate to provide a barrier to prevent diffusion between adjacent materials.
Conventional barrier layers include materials such as titanium nitride (TiN), tantalum nitride (TaN) and tungsten nitride (TuN). The materials are deposited using processes such as physical vapor deposition (PVD) (e.g., ionized metal plasma PVD, sputtering, etc.) and chemical vapor deposition (CVD) (e.g., plasma enhanced CVD, metal-organic CVD, etc.). TiN layers, in particular, have been widely employed in semiconductor manufacturing as a “diffusion barrier” layer; that is, it is placed between two metal or semiconductor layers to prevent intermixing and undesired interactions, while still permitting electrical current to flow. TiN is a hard, dense, refractory material with unusually high electrical conductivity. Ideally, the processes that are used to deposit the TiN barrier layer will not impact the reliability of the resulting IC formed and generate a high reactive sticking coefficient (Rc) for TiN to the silicon (Si) substrate.
Conventional methods for depositing TiN have been shown to adversely impact the reliability of the resulting ICs formed. This is due to a variety of factors including: impurities resulting from the deposition processes themselves, and cross reactions between the non-TiN material layers on the Si substrate and byproducts from the deposition processes. Additionally, the low to moderate Rc of these traditional processes do not always result in uniform TiN layers being deposited across the Si substrate surfaces.